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| XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT AUGUST 2006 REV. 1.0.0 GENERAL DESCRIPTION The XRT83SL216 is a fully integrated 16-channel E1 short-haul LIU which optimizes system cost and performance by offering key design features. The XRT83SL216 operates from a single 3.3V power supply. The LIU features are programmed through a standard serial microprocessor interface. EXAR's LIU has patented high impedance circuits that allow the transmitter outputs and receiver inputs to be placed in a high impedance mode when experiencing a power failure or when the LIU is powered off. Additional features include TAOS for transmit and receive, RLOS, LCV, on chip Jitter Attenuator, AIS detector, and diagnostic loopback modes. FIGURE 1. BLOCK DIAGRAM OF THE XRT83SL216 APPLICATIONS * * * * * * * * ISDN Primary Rate Interface CSU/DSU E1 Interface E1 LAN/WAN Routers Public Switching Systems and PBX Interfaces E1 Multiplexer and Channel Banks Integrated Multi-Service Access Platforms (IMAPs) Integrated Access Devices (IADs) Inverse Multiplexing for ATM (IMA) Wireless Base Stations 1 of 16 Channels TCLK TPOS TNEG HDB3 Encoder Timing Control Tx Pulse Shaper Line Driver TTIP TRING Analog Loopback Remote Loopback Jitter Attenuator (Rx or Tx) Digital Loopback RCLK RPOS RNEG/LCV HDB3 Decoder Clock & Data Recovery Peak Detector & Slicer Rx Equalizer RTIP RRING RLOS AIS & LOS Detector JASEL0 JASEL1 TDI TMS TCK JTAG Serial Microprocessor Interface Internal Clock Generator TxOE TRST TDO Reset SCLK Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com SDO SDI MCLK INT CS XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT FEATURES REV. 1.0.0 * Fully integrated 16-Channel short haul transceivers for E1 (2.048MHz) applications * Tri-State on a per channel basis for the transmit selection * Crystal-Less digital jitter attenuators (JA) with 32-Bit or 64-Bit FIFO for the receive or transmit paths * Transmit outputs and receive inputs stay in the High Impedance mode upon power failure * Support for automatic protection switching * RLOS/AIS according to ITU-T G.775 or ETSI-300-233 * On-Chip HDB3 encoder/decoder for each channel * On-Chip digital clock recovery circuit for high input jitter tolerance * On-Chip per channel driver failure monitoring circuit * On-Chip transmit pulse shaper for CEPT 75 and 120 line terminations * High receiver interference immunity * Transmit return loss meets or exceeds ETS1 300-166 * Meets or exceeds ITU G.703, G,775, G.736 and G.823 * Line code error and bipolar violation detection * Transmit all ones (TAOS) for the Transmit and Receive Outputs * Supports local analog, remote, and digital loopback modes * Supports gapped clocks for mapper/multiplexer applications * Low Power dissipation * Single 3.3V supply operation (3V to 5V I/O tolerant) * 289-Pin STBGA package * -40C to +85C Temperature Range PRODUCT ORDERING INFORMATION PRODUCT NUMBER XRT83SL216IB PACKAGE TYPE 289 Ball STBGA OPERATING TEMPERATURE RANGE -40C to +85C 2 XRT83SL216 REV. 1.0.0 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT FIGURE 2. PIN OUT FOR THE XRT83SL216 (BOTTOM VIEW) (See pin list for pin names and function) XRT83SL216 A B C D E F G H J K L M N P R T U 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 3 XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 TABLE OF CONTENTS GENERAL DESCRIPTION ................................................................................................ 1 APPLICATIONS .......................................................................................................................................... 1 FIGURE 1. BLOCK DIAGRAM OF THE XRT83SL216 ........................................................................................................................... 1 FEATURES ..................................................................................................................................................... 2 PRODUCT ORDERING INFORMATION ................................................................................................. 2 FIGURE 2. PIN OUT FOR THE XRT83SL216 (BOTTOM VIEW) ............................................................................................................. 3 TABLE OF CONTENTS ............................................................................................................ I PIN DESCRIPTIONS ......................................................................................................... 4 SERIAL MICROPROCESSOR INTERFACE ........................................................................................................... 4 RECEIVER SECTION....................................................................................................................................... 5 TRANSMITTER SECTION ................................................................................................................................. 8 CONTROL FUNCTION ................................................................................................................................... 11 JTAG SECTION........................................................................................................................................... 11 POWER AND GROUND ................................................................................................................................. 12 1.0 RECEIVE PATH LINE INTERFACE....................................................................................................... 15 FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH LINE TERMINATION (RTIP/RRING).................................................. 15 1.1 PEAK DETECTOR/DATA SLICER.................................................................................................................... 15 1.2 CLOCK AND DATA RECOVERY ...................................................................................................................... 15 FIGURE 4. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK .............................................................................................. 15 FIGURE 5. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK ............................................................................................ 15 TABLE 1: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG .......................................................................................................... 16 1.3 RECEIVE SENSITIVITY ..................................................................................................................................... 16 FIGURE 6. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY........................................................................................ 16 1.4 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ............................................................... 16 1.4.1 RLOS (RECEIVER LOSS OF SIGNAL)........................................................................................................................ 17 1.4.2 AIS (ALARM INDICATION SIGNAL) ............................................................................................................................ 17 1.4.3 LCV (LINE CODE VIOLATION DETECTION) .............................................................................................................. 17 1.5 RECEIVE JITTER ATTENUATOR..................................................................................................................... 17 1.6 HDB3 DECODER ............................................................................................................................................... 17 1.7 ARAOS (AUTOMATIC RECEIVE ALL ONES).................................................................................................. 18 FIGURE 7. SIMPLIFIED BLOCK DIAGRAM OF THE ARAOS FUNCTION ................................................................................................ 18 1.8 RPOS/RNEG/RCLK ........................................................................................................................................... 18 FIGURE 8. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN ..................................................................................... 18 FIGURE 9. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN........................................................................................ 18 2.0 TRANSMIT PATH LINE INTERFACE .................................................................................................... 19 FIGURE 10. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH ................................................................................................... 19 2.1 TCLK/TPOS/TNEG DIGITAL INPUTS............................................................................................................... 19 FIGURE 11. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK ............................................................................................... 19 FIGURE 12. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK ................................................................................................. 19 TABLE 2: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG ........................................................................................................... 20 2.2 HDB3 ENCODER ............................................................................................................................................... 20 TABLE 3: EXAMPLES OF HDB3 ENCODING ...................................................................................................................................... 20 2.3 TRANSMIT JITTER ATTENUATOR .................................................................................................................. 20 TABLE 4: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS .................................................................................... 20 2.4 TAOS (TRANSMIT ALL ONES)......................................................................................................................... 21 FIGURE 13. TAOS (TRANSMIT ALL ONES) ...................................................................................................................................... 21 2.5 ATAOS (AUTOMATIC TRANSMIT ALL ONES) ............................................................................................... 21 FIGURE 14. SIMPLIFIED BLOCK DIAGRAM OF THE ATAOS FUNCTION............................................................................................... 21 3.0 APPLICATIONS ..................................................................................................................................... 22 3.1 LOOPBACK DIAGNOSTICS ............................................................................................................................. 22 3.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................... FIGURE 15. SIMPLIFIED BLOCK DIAGRAM OF LOCAL ANALOG LOOPBACK ......................................................................................... 3.1.2 REMOTE LOOPBACK .................................................................................................................................................. FIGURE 16. SIMPLIFIED BLOCK DIAGRAM OF REMOTE LOOPBACK .................................................................................................... 3.1.3 DIGITAL LOOPBACK ................................................................................................................................................... FIGURE 17. SIMPLIFIED BLOCK DIAGRAM OF DIGITAL LOOPBACK ..................................................................................................... 22 22 22 22 23 23 3.2 INTERFACING THE TRANSMIT SECTION OF THE XRT83L216 TO THE LINE ............................................ 23 FIGURE 18. INTERFACING THE XRT83L216 TO THE LINE FOR 75W APPLICATIONS (1 CHANNEL SHOWN) .......................................... 23 FIGURE 19. INTERFACING THE XRT83L216 TO THE LINE FOR 120 W APPLICATIONS (1CHANNEL SHOWN) ....................................... 24 I XRT83SL216 REV. 1.0.0 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT The following Ferrite Bead is Recommended for Use .............................................................................................. 24 The following Transformer is Recommended for Use .............................................................................................. 25 4.0 SERIAL MICROPROCESSOR INTERFACE BLOCK ........................................................................... 26 FIGURE 20. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE ................................................................. 26 FIGURE 21. MICROPROCESSOR SERIAL INTERFACE STRUCTURE ..................................................................................................... 26 FIGURE 22. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE ................................................................................ 27 TABLE 5: MICROPROCESSOR SERIAL INTERFACE TIMINGS ( TA = 250C, VDD=3.3V 5% AND LOAD = 10PF) .................................. 27 TABLE 6: MICROPROCESSOR REGISTER DESCRIPTION .................................................................................................................... 28 TABLE 7: MICROPROCESSOR REGISTER 0X00H BIT DESCRIPTION ................................................................................................... 30 TABLE 8: MICROPROCESSOR REGISTERS 0X01H &0X02H BIT DESCRIPTION .................................................................................... 31 TABLE 9: MICROPROCESSOR REGISTER 0X03H BIT DESCRIPTION ................................................................................................... 32 TABLE 10: MICROPROCESSOR REGISTERS 0X04H & 0X05H BIT DESCRIPTION ................................................................................. 32 TABLE 11: MICROPROCESSOR REGISTER BIT DESCRIPTION ............................................................................................................ 32 TABLE 12: MICROPROCESSOR REGISTER BIT DESCRIPTION ............................................................................................................ 34 TABLE 13: MICROPROCESSOR REGISTER BIT DESCRIPTION ............................................................................................................ 34 ELECTRICAL CHARACTERISTICS............................................................................... 36 TABLE 14: ABSOLUTE MAXIMUM RATINGS ....................................................................................................................................... 36 TABLE 15: DC DIGITAL INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS .................................................................................... 36 TABLE 16: AC ELECTRICAL CHARACTERISTICS ............................................................................................................................... 36 TABLE 17: POWER CONSUMPTION .................................................................................................................................................. 36 TABLE 18: RECEIVER ELECTRICAL CHARACTERISTICS ..................................................................................................................... 37 TABLE 19: E1 TRANSMITTER ELECTRICAL CHARACTERISTICS .......................................................................................................... 38 ORDERING INFORMATION ........................................................................................... 39 PACKAGE DIMENSIONS ............................................................................................... 39 FIGURE 23. 15X15MM 289 BALL STBGA........................................................................................................................................ 39 REVISION HISTORY ..................................................................................................................................... 40 II XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 PIN DESCRIPTIONS HOST MODE INTERFACE SERIAL MICROPROCESSOR INTERFACE NAME CS PIN J4 TYPE I DESCRIPTION Chip Select Input Active low signal. This signal enables the serial microprocessor interface by pulling chip select "Low". The serial interface is disabled when the chip select signal returns "High". Serial Clock Input The serial clock input samples SDI on the rising edge and updates SDO on the falling edge. See the Serial Microprocessor section of this datasheet for more details. Serial Data Input The serial data input pin is used to supply an address and data string to program the internal registers within the device. See the Serial Microprocessor section of this datasheet for more details. Serial Data Output The serial data output pin is used to retrieve the internal contents of a selected register in readback mode. See the Microprocessor section of this datasheet for more details. Hardware Reset Input Active low signal. When this pin is pulled "Low" for more than 10S, all internal registers and state machines are set to their default state. NOTE: Internally pulled "High" with 50k. INT K4 O Interrupt Output Active low signal. This signal is asserted "Low" when a change in alarm status occurs. Once the status registers have been read, the interrupt pin will return "High". GIE (Global Interrupt Enable) must be set "High" in the appropriate global register to enable interrupt generation. NOTE: This pin is an open-drain output that requires an external 10K pull-up resistor. SCLK J5 I SDI K5 I SDO L5 O Reset J6 I 4 XRT83SL216 REV. 1.0.0 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT RECEIVER SECTION NAME RLOS15 RLOS14 RLOS13 RLOS12 RLOS11 RLOS10 RLOS9 RLOS8 RLOS7 RLOS6 RLOS5 RLOS4 RLOS3 RLOS2 RLOS1 RLOS0 RCLK15 RCLK14 RCLK13 RCLK12 RCLK11 RCLK10 RCLK9 RCLK8 RCLK7 RCLK6 RCLK5 RCLK4 RCLK3 RCLK2 RCLK1 RCLK0 PIN B10 D11 F10 B12 T12 T11 M10 R10 U8 R7 M8 T6 B6 B7 F8 C8 A10 A11 E10 A12 U12 U11 N10 P10 T8 P7 N8 U6 A6 A7 E8 D8 TYPE O DESCRIPTION Receive Loss of Signal When a receive loss of signal occurs, the RLOS pin will go "High" for a minimum of one RCLK cycle. RLOS will remain "High" until the loss of signal condition clears. See the Receive Loss of Signal section of this datasheet for more details. O Receive Clock Output RCLK is the recovered clock from the incoming data stream. If the incoming signal is absent, RCLK maintains its timing by using an internal master clock as its reference. RPOS/RNEG data can be updated on either edge of RCLK selected by RCLKinv in the appropriate channel register. 5 XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT RECEIVER SECTION NAME RPOS15 RPOS14 RPOS13 RPOS12 RPOS11 RPOS10 RPOS9 RPOS8 RPOS7 RPOS6 RPOS5 RPOS4 RPOS3 RPOS2 RPOS1 RPOS0 RNEG/LCV15 RNEG/LCV14 RNEG/LCV13 RNEG/LCV12 RNEG/LCV11 RNEG/LCV10 RNEG/LCV9 RNEG/LCV8 RNEG/LCV7 RNEG/LCV6 RNEG/LCV5 RNEG/LCV4 RNEG/LCV3 RNEG/LCV2 RNEG/LCV1 RNEG/LCV0 PIN C10 C11 E11 C12 R12 R11 M11 T10 R8 T7 N7 R6 C6 C7 F7 A8 D10 B11 F11 D12 P12 P11 N11 U10 P8 U7 M7 P6 D6 D7 E7 B8 TYPE O DESCRIPTION RPOS/RDATA Output Receive digital output pin. In dual rail mode, this pin is the receive positive data output. In single rail mode, this pin is the receive non-return to zero (NRZ) data output. REV. 1.0.0 O RNEG/LCV Output In dual rail mode, this pin is the receive negative data output. In single rail mode, this pin is a Line Code Violation indicator. If a line code violation or a bipolar violation occur, the LCV pin will pull "High" for a minimum of one RCLK cycle. LCV will remain "High" until there are no more violations. If AMI coding is selected, every bipolar violation will cause this pin to go "High". 6 XRT83SL216 REV. 1.0.0 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT RECEIVER SECTION NAME RTIP15 RTIP14 RTIP13 RTIP12 RTIP11 RTIP10 RTIP9 RTIP8 RTIP7 RTIP6 RTIP5 RTIP4 RTIP3 RTIP2 RTIP1 RTIP0 RRING15 RRING14 RRING13 RRING12 RRING11 RRING10 RRING9 RRING8 RRING7 RRING6 RRING5 RRING4 RRING3 RRING2 RRING1 RRING0 PIN B17 D17 F17 H17 K17 M17 P17 T17 T1 P1 M1 K1 H1 F1 D1 B1 C17 E17 G17 J17 L17 N17 R17 T16 T2 R1 N1 L1 J1 G1 E1 C1 TYPE I DESCRIPTION Receive Differential Tip Input RTIP is the positive differential input from the line interface. Along with the RRING signal, these pins should be coupled to a 2:1 transformer for proper operation. I Receive Differential Ring Input RRING is the negative differential input from the line interface. Along with the RTIP signal, these pins should be coupled to a 2:1 transformer for proper operation. 7 XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT TRANSMITTER SECTION NAME TxOE PIN K14 TYPE I DESCRIPTION Transmit Output Enable Upon power up, the transmitters are tri-stated. Enabling the transmitters is selected through the serial microprocessor interface by programming the appropriate channel register if this pin is pulled "High". If the TxOE pin is pulled "Low", all 16 transmitters are tri-stated. NOTE: TxOE is ideal for redundancy applications. See the Redundancy Applications Section of this datasheet for more details. Internally pulled "Low" with a 50k resistor. REV. 1.0.0 TCLK15 TCLK14 TCLK13 TCLK12 TCLK11 TCLK10 TCLK9 TCLK8 TCLK7 TCLK6 TCLK5 TCLK4 TCLK3 TCLK2 TCLK1 TCLK0 TPOS15 TPOS14 TPOS13 TPOS12 TPOS11 TPOS10 TPOS9 TPOS8 TPOS7 TPOS6 TPOS5 TPOS4 TPOS3 TPOS2 TPOS1 TPOS0 A14 D13 C14 E14 N14 P13 U16 R13 R5 U2 P5 N4 E4 A3 F5 C5 B13 E13 A15 F13 M14 N13 U15 T13 T5 U3 N5 M4 D4 B4 D5 B5 I Transmit Clock Input TCLK is the input facility clock used to sample the incoming TPOS/TNEG data. TPOS/TNEG data can be sampled on either edge of TCLK selected by TCLKinv in the appropriate channel register. I TPOS/TDATA Input Transmit digital input pin. In dual rail mode, this pin is the transmit positive data input. In single rail mode, this pin is the transmit non-return to zero (NRZ) data input. 8 XRT83SL216 REV. 1.0.0 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT TRANSMITTER SECTION NAME TNEG15 TNEG14 TNEG13 TNEG12 TNEG11 TNEG10 TNEG9 TNEG8 TNEG7 TNEG6 TNEG5 TNEG4 TNEG3 TNEG2 TNEG1 TNEG0 PIN A13 C13 B14 D14 L14 M13 U14 U13 U5 U4 M5 L4 C4 A4 E5 A5 TYPE I DESCRIPTION Transmit Negative Data Input In dual rail mode, this pin is the transmit negative data input. In single rail mode, this pin can be tied to ground. 9 XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT TRANSMITTER SECTION NAME TTIP15 TTIP14 TTIP13 TTIP12 TTIP11 TTIP10 TTIP9 TTIP8 TTIP7 TTIP6 TTIP5 TTIP4 TTIP3 TTIP2 TTIP1 TTIP0 TRING15 TRING14 TRING13 TRING12 TRING11 TRING10 TRING9 TRING8 TRING7 TRING6 TRING5 TRING4 TRING3 TRING2 TRING1 TRING0 PIN B15 D15 F15 H15 K15 M15 P15 T14 T4 P3 M3 K3 H3 F3 D3 B3 C15 E15 G15 J15 L15 N15 R15 R14 R4 R3 N3 L3 J3 G3 E3 C3 TYPE O DESCRIPTION Transmit Differential Tip Output TTIP is the positive differential output to the line interface. Along with the TRING signal, these pins should be coupled to a 1:2 step up transformer for proper operation. REV. 1.0.0 O Transmit Differential Ring Output TRING is the negative differential output to the line interface. Along with the TTIP signal, these pins should be coupled to a 1:2 step up transformer for proper operation. 10 XRT83SL216 REV. 1.0.0 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT CONTROL FUNCTION NAME JASEL0 JASEL1 PIN G13 H13 TYPE I DESCRIPTION Jitter Attenuator Select: The Jitter Attenuator can be slected to be in the Transmit or Receive path. JASEL1 0 0 1 1 JASEL0 0 1 0 1 Jitter Attenuator State JA Disabled JA in Tx Path JA in Rx Path JA Select is enabled through P Control NOTE: Internally pulled "High" with a 50k resistor. MCLK L6 I Master Clock Input This pin is used as the internal reference to the LIU. This clock must be 2.048MHz +/-50ppm. JTAG SECTION NAME TCK TDI PIN G5 G4 TYPE I I DESCRIPTION JTAG Test Clock input, Boundary Scan Clock input: JTAG Test Data input, Boundary Scan Test Data Input: NOTE: Internally pulled "High" with a 50k resistor. TDO H5 O JTAG Test Data output: Boundary Scan Test Data Output: JTAG Test Mode Select, Boundary Scan Test Mode Select input pin: NOTE: Internally pulled "High" with a 50k resistor. TRST H4 I JTAG Test Mode Reset, Boundary Scan Mode Reset Input pin: NOTE: This input pin should be pulled "Low" for normal operation. Internally pulled "High" with a 50k resistor. TMS G6 I 11 XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT POWER AND GROUND NAME TVDD15 TVDD14 TVDD13 TVDD12 TVDD11 TVDD10 TVDD9 TVDD8 TVDD7 TVDD6 TVDD5 TVDD4 TVDD3 TVDD2 TVDD1 TVDD0 RefVDD AVDD_pll PIN C16 E16 G16 J16 L16 N16 R16 P14 P4 R2 N2 L2 J2 G2 E2 C2 K12 K6 TYPE PWR DESCRIPTION Transmit Analog Power Supply (3.3V 5%) TVDD can be shared with DVDD. However, it is recommended that TVDD be isolated from the analog power supply RVDD. For best results, use an internal power plane for isolation. If an internal power plane is not available, a ferrite bead can be used. Each power supply pin should be bypassed to ground through an external 0.1F capacitor and a 10F capacitor. REV. 1.0.0 PWR Analog Power Supply (3.3V 5%) Thes analog supply pins should not be shared with other power supplies. It is recommended that they be isolated from the digital power supply, DVDD. For best results, use an internal power plane for isolation. If an internal power plane is not available, a ferrite bead can be used. Each power supply pin should be bypassed to ground through an external 0.1F capacitor. Digital Power Supply (3.3V 5%) DVDD should be isolated from the analog power supplies except for TVDD. For best results, use an internal power plane for isolation. If an internal power plane is not available, a ferrite bead can be used. Every two DVDD power supply pins should be bypassed to ground through at least one 0.1F capacitor. DVDD A2 A17 C9 D9 H6 H12 P9 R9 E9 F6 F9 F12 M6 M9 M12 N9 PWR RVDD_1 PWR RVDD_2 Receive Power Supply (3.3V 5%) RVDD should be isolated from the digital power supplies. For best results, use an internal power plane for isolation. If an internal power plane is not available, a ferrite bead can be used. Each power supply pin should be bypassed to ground through at least one 0.1F capacitor and a 10F capacitor. 12 XRT83SL216 REV. 1.0.0 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT POWER AND GROUND NAME TGND15 TGND14 TGND13 TGND12 TGND11 TGND10 TGND9 TGND8 TGND7 TGND6 TGND5 TGND4 TGND3 TGND2 TGND1 TGND0 DGND PIN B16 D16 F16 H16 K16 M16 P16 T15 T3 P2 M2 K2 H2 F2 D2 B2 A1 A9 A16 B9 T9 U1 U9 U17 TYPE GND DESCRIPTION Transmit Analog Ground It's recommended that all ground pins of this device be tied together and to a ground plane. GND Digital Ground It's recommended that all ground pins of this device be tied together and to a ground plane. 13 XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT POWER AND GROUND NAME AGND PIN G7 G8 G9 G10 G11 H7 H8 H9 H10 H11 J7 J8 J9 J10 J11 K7 K8 K9 K10 K11 L7 L8 L9 L10 L11 J14 E6 E12 F4 F14 G12 G14 H14 J12 J13 K13 L12 L13 N6 N12 TYPE GND DESCRIPTION Analog Ground It's recommended that all ground pins of this device be tied together and to a ground plane. REV. 1.0.0 NOTE: J14 is a factory test pin and MUST be grounded for normal operation. NC NC No Connects 14 XRT83SL216 REV. 1.0.0 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 1.0 RECEIVE PATH LINE INTERFACE The receive path consists of 16 independent E1 receivers. The following section describes the complete receive path from RTIP/RRING inputs to RCLK/RPOS/RNEG outputs. A simplified block diagram of the receive path is shown in Figure 3. FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH LINE TERMINATION (RTIP/RRING) RCLK RPOS RNEG HDB3 Decoder Rx Jitter Attenuator Clock & Data Recovery Rx Equalizer & Peak Detector RTIP RRING 1.1 Peak Detector/Data Slicer In the receive path, the line signal is coupled into the RTIP and RRing pins via a 2:1 transformer and are converted into digital pulses by an equalizer and an adaptive data slicer. Clock and data signals are recovered from the output of the slicer with the help of a digital PLL that provides excellent jitter accommodation for high input jitter tolerance. 1.2 Clock and Data Recovery The receive clock (RCLK) is recovered by the clock and data recovery circuitry. An internal PLL locks on the incoming data stream and outputs a clock that's in phase with the incoming signal. In the absence of an incoming signal, RCLK maintains its timing by using MCLK as its reference. The recovered data can be updated on either edge of RCLK. By default, data is updated on the rising edge of RCLK. To update data on the falling edge of RCLK, set RCLKinv to "1" in the appropriate global register. Figure 4 is a timing diagram of the receive data updated on the rising edge of RCLK. Figure 5 is a timing diagram of the receive data updated on the falling edge of RCLK. The timing specifications are shown in Table 1. FIGURE 4. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK R DY R C LK R R C LK F R C LK RPOS or RNEG R OH FIGURE 5. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK RDY RCLKF RCLKR RCLK RPOS or RNEG ROH 15 XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT TABLE 1: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG PARAMETER RCLK Duty Cycle Receive Data Setup Time Receive Data Hold Time RCLK to Data Delay RCLK Rise Time (10% to 90%) with 25pF Loading RCLK Fall Time (90% to 10%) with 25pF Loading SYMBOL RCDU RSU RHO RDY RCLKR RCLKF MIN 45 150 150 TYP 50 MAX 55 40 40 40 UNITS % ns ns ns ns ns REV. 1.0.0 NOTE: VDD=3.3V 5%, TA=25C, Unless Otherwise Specified 1.3 Receive Sensitivity To meet short haul requirements, the XRT83SL216 can accept E1 signals that have been attenuated by 11dB of flat loss in E1 mode. The test configuration for measuring the receive sensitivity is shown in Figure 6. FIGURE 6. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY Tx Ne twork Analyze r Rx Flat Loss Tx XRT83SL216 16-Channe l Short Haul LIU Exte rnalLoopback Rx E1 = PRBS 2 15 - 1 1.4 General Alarm Detection and Interrupt Generation The receive path detects RLOS and AIS. These alarms can be individually masked to prevent the alarm from triggering an interrupt. To enable interrupt generation, the Global Interrupt Enable (GIE) bit must be set "High" in the appropriate global register. Any time a change in status occurs (if the alarms are enabled), the interrupt pin will pull "Low" to indicate an alarm has occurred. Once the status registers have been read, the INT pin will return "High". The status registers are Reset Upon Read (RUR). NOTE: The interrupt pin is an Open-Drain output that requires a 10k pull-up resistor. 16 XRT83SL216 REV. 1.0.0 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT RLOS (Receiver Loss of Signal) 1.4.1 The XRT83SL216 supports both G.775 or ETSI-300-233 RLOS detection scheme. In G.775 mode, RLOS is declared when the received signal is less than 320mV for more than 32 consecutive pulse periods (typical). The device clears RLOS when the receive signal achieves 12.5% ones density with no more than 15 consecutive zeros in a 32 bit sliding window and the signal level exceeds 550mV (typical). In ETSI-300-233 mode the device declares RLOS when the input level drops below 320mV (typical) for more than 2048 pulse periods (1msec). The device clears RLOS when the receive signal achieves 12.5% ones density with no more than 15 consecutive zeros in a 32 bit sliding window and the signal level exceeds 550mV (typical). 1.4.2 AIS (Alarm Indication Signal) The XRT83SL216 adheres to ITU-T G.775 or ETSI-300-233 specifications for an all ones pattern detection by programming the appropriate channel register. The alarm indication signal is set to "1" if an all ones pattern is detected. In G.775 mode, AIS is defined as 2 or less zeros in 2 consecutive double frame (512-bit window) periods. AIS will clear when the incoming signal has 3 or more zeros in the same time period. In ETSI-300-233 mode, AIS is defined as less than 3 zeros in a 512-bit window. 1.4.3 LCV (Line Code Violation Detection) In HDB3 mode, the LCV pin will be set to "High" if the receiver detects excessive zero's, bipolar violations or HDB3 code violations. If the device is configured in AMI mode, any bipolar violations will cause the LCV pin to go "High". 1.5 Receive Jitter Attenuator The jitter attenuator can be configured in the receive path to reduce phase and frequency jitter in the recovered clock. The jitter attenuator uses a data FIFO (First In First Out) with a programmable depth of 32-bit or 64-bit. If the LIU is used for line synchronization (loop timing systems), the JA should be enabled. When the Read and Write pointers of the FIFO are within 2-Bits of over-flowing or under-flowing, the bandwidth of the jitter attenuator is widened to track the short term input jitter, thereby avoiding data corruption. When this condition occurs, the jitter attenuator will not attenuate input jitter until the Read/Write pointer's position is outside the 2Bit window. The JA has a typical clock delay equal to 1/2 of the FIFO bit depth. NOTE: If the LIU is used in a multiplexer/mapper application where stuffing bits are typically removed, the JA can be configured in the transmit path to smooth out the gapped clock. See the Transmit Section of this datasheet. 1.6 HDB3 Decoder In single rail mode, RPOS is the output of decoded AMI or HDB3 signals and RNEG is the LCV output. HDB3 data is defined as any block of 4 successive zeros replaced with OOOV or BOOV, so that two successive V pulses are of opposite polarity to acheive zero DC offset. If the HDB3 decoder is selected, the receive path removes the V and B pulses so that the original data is output to RPOS. 17 XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 1.7 ARAOS (Automatic Receive All Ones) REV. 1.0.0 If ARAOS is enabled in the appropriate channel register and an RLOS condition occurs, the Receiver outputs will generate an All Ones pattern using MCLK as reference. When RLOS clears, the All Ones pattern ends and the Receive path returns to normal operation. FIGURE 7. SIMPLIFIED BLOCK DIAGRAM OF THE ARAOS FUNCTION RPOS RNEG Rx All "1's" Generator Timing derived from MCLK ARAOS RLOS 1.8 RPOS/RNEG/RCLK The digital output data can be programmed to either single rail or dual rail formats. Figure 8 is a timing diagram of a repeating "0011" pattern in single-rail mode. Figure 9 is a timing diagram of the same fixed pattern in dual rail mode. FIGURE 8. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN RCLK RPOS 0 0 1 1 0 FIGURE 9. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN RCLK RPOS RNEG 0 1 0 0 1 18 XRT83SL216 REV. 1.0.0 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 2.0 TRANSMIT PATH LINE INTERFACE The transmit path consists of 16 independent E1 transmitters. The following section describes the complete transmit path from TCLK/TPOS/TNEG inputs to TTIP/TRING outputs. A simplified block diagram of the transmit path is shown in Figure 10. FIGURE 10. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH TCLK TPOS TNEG TTIP Tx Pulse Shaper Line Driver TRING HDB3 Encoder Tx Jitter Attenuator Timing Control 2.1 TCLK/TPOS/TNEG Digital Inputs In dual rail mode, TPOS and TNEG are the digital inputs for the transmit path. In single rail mode, TNEG can be tied to ground. The XRT83SL216 can be programmed to sample the inputs on either edge of TCLK. By default, data is sampled on the falling edge of TCLK. To sample data on the rising edge of TCLK, set TCLKinv to "1" in the appropriate global register. Figure 11 is a timing diagram of the transmit input data sampled on the falling edge of TCLK. Figure 12 is a timing diagram of the transmit input data sampled on the rising edge of TCLK. The timing specifications are shown in Table 2. FIGURE 11. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK TCLKR TCLKF TCLK TPOS or TNEG TSU THO FIGURE 12. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK TCLKF TCLKR TCLK TPOS or TNEG TSU THO 19 XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT TABLE 2: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG PARAMETER SYMBOL MIN TYP MAX UNITS REV. 1.0.0 TCLK Duty Cycle Transmit Data Setup Time Transmit Data Hold Time TCLK Rise Time (10% to 90%) TCLK Fall Time (90% to 10%) TCDU TSU THO TCLKR TCLKF 30 50 30 - 50 - 70 40 40 % ns ns ns ns NOTE: VDD=3.3V 5%, TA=25C, Unless Otherwise Specified 2.2 HDB3 Encoder In single rail mode, the LIU can encode the TPOS input signal to AMI or HDB3 data. If HDB3 encoding is selected, any sequence with four or more consecutive zeros in the input will be replaced with 000V or B00V, where "B" indicates a pulse conforming to the bipolar rule and "V" representing a pulse violating the rule. An example of HDB3 encoding is shown in Table 3. TABLE 3: EXAMPLES OF HDB3 ENCODING NUMBER OF PULSES BEFORE NEXT 4 ZEROS Input HDB3 (Case 1) HDB3 (Case 2) Odd Even 0000 000V B00V 2.3 Transmit Jitter Attenuator The XRT83SL216 LIU is ideal for multiplexer or mapper applications where the network data crosses multiple timing domains. As the higher data rates are de-multiplexed to E1 data, stuffing bits are typically removed which can leave gaps in the incoming data stream. The JA can be configured in the transmit path with a 32-Bit or 64-Bit FIFO that is used to smooth the gapped clock into a steady E1 output. The maximum gap width the JA in the Transmit path can tolerate is shown in Table 4. TABLE 4: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS FIFO DEPTH MAXIMUM GAP WIDTH 32-Bit 64-Bit 20 UI 50 UI NOTE: If the LIU is used in a loop timing system, the JA should be configured in the receive path. See the Receive Section of this datasheet. 20 XRT83SL216 REV. 1.0.0 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 2.4 TAOS (Transmit All Ones) The XRT83SL216 has the ability to transmit all ones on a per channel basis by programming the appropriate channel register. If TAOS is enabled, the Transmitter outputs will generate an All Ones pattern regardless of the Transmit Input data. The Remote Loop Back mode has priority over TAOS. Figure 13 is a diagram showing the all ones signal at TTIP and TRING. FIGURE 13. TAOS (TRANSMIT ALL ONES) 1 TAOS 1 1 2.5 ATAOS (Automatic Transmit All Ones) ATAOS is used to generate an All Ones signal only when an RLOS condition occurs. If ATAOS is enabled, any channel that experiences an RLOS condition will automatically cause the transmitter on that channel to send an All Ones Pattern to the line using MCLK as reference. When RLOS clears, the All Ones pattern ends and the Transmit path returns to normal operation. FIGURE 14. SIMPLIFIED BLOCK DIAGRAM OF THE ATAOS FUNCTION TTIP Tx TRING All "1's" Generator Timing derived from MCLK ATAOS RLOS 21 XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 3.0 APPLICATIONS This applications section describes system considerations along with references to application notes available for reference where applicable. 3.1 Loopback Diagnostics REV. 1.0.0 The XRT83SL216 supports several loopback modes for diagnostic testing. The following section describes the local analog loopback, remote loopback, and digital loopback. 3.1.1 Local Analog Loopback With local analog loopback activated, the transmit output data at TTIP/TRING is internally looped back to the analog inputs at RTIP/RRING. External inputs at RTIP/RRING are ignored while valid transmit output data continues to be sent to the line. A simplified block diagram of local analog loopback is shown in Figure 15. FIGURE 15. SIMPLIFIED BLOCK DIAGRAM OF LOCAL ANALOG LOOPBACK TAOS TCLK TPOS TNEG Timing Control TTIP TRING Encoder JA Tx RCLK RPOS RNEG Decoder JA Data and Clock Recovery Rx RTIP RRING NOTE: TAOS takes priority over the transmit input data at TPOS/TNEG. 3.1.2 Remote Loopback With remote loopback activated, the receive input data at RTIP/RRING is internally looped back to the transmit output data at TTIP/TRING. The transmit input data at TCLK/TPOS/TNEG are ignored while valid receive output data continues to be sent to the system. A simplified block diagram of remote loopback is shown in Figure 16. FIGURE 16. SIMPLIFIED BLOCK DIAGRAM OF REMOTE LOOPBACK TAOS TCLK TPOS TNEG Timing Control TTIP TRING Encoder JA Tx RCLK RPOS RNEG Decoder JA Data and Clock Recovery Rx RTIP RRING NOTE: Remote Loop Back takes priority over TAOS. 22 XRT83SL216 REV. 1.0.0 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT Digital Loopback 3.1.3 With digital loopback activated, the transmit input data at TCLK/TPOS/TNEG is looped back to the receive output data at RCLK/RPOS/RNEG. The receive input data at RTIP/RRING is ignored while valid transmit output data continues to be sent to the line. A simplified block diagram of digital loopback is shown in Figure 17. FIGURE 17. SIMPLIFIED BLOCK DIAGRAM OF DIGITAL LOOPBACK TAOS TCLK TPOS TNEG Timing Control TTIP TRING Encoder JA Tx RCLK RPOS RNEG Decoder JA Data and Clock Recovery Rx RTIP RRING 3.2 Interfacing the Transmit Section of the XRT83L216 to the Line ITU-T G.703 specifies that the E1 line signal can be transmitted over coaxial cable and terminated with 75 or transmitted over twisted-pair and terminated with 120. In both applications (e.g., 75 or 120, the user is advised to interface the Transmitter to the Line, in the manner as depicted in Figure 18 and Figure 19, respectively. FIGURE 18. INTERFACING THE XRT83L216 TO THE LINE FOR 75 APPLICATIONS (1 CHANNEL SHOWN) 75 Coax 2 :1 RPOS/RData RTIP RNEG/LCV RClk +3.3 V 75 Signal Source 18.7 Rx Input RVDD TVDD 0.1 F 0.1 F RRING AVDD 0.1 F 10F 75 Coax 2:1 TTIP 9.1 TGND AGND R Load 75 Tx Output TNEG/CODE 9.1 TRING TClk TPOS/TData Ferrite Bead 23 XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT FIGURE 19. INTERFACING THE XRT83L216 TO THE LINE FOR 120 APPLICATIONS (1CHANNEL SHOWN) 120 Twisted Pair REV. 1.0.0 2 :1 RPOS/RData RTIP RNEG/LCV RClk +3.3 V 120 Signal Source 30 Rx Input TVDD AVDD RRING RVDD 0.1 F 0.1 F 0.1 F 120 Twisted Pair 10F 2:1 TTIP 9.1 TGND AGND R Load 120 Tx Output TNEG/CODE 9.1 TRING TClk TPOS/TData Ferrite Bead THE FOLLOWING FERRITE BEAD IS RECOMMENDED FOR USE PART NUMBER HZ0402A601r-00 VENDOR Steward TYP. IMPEDANCE @ 100MHZ 600 TYP. IMPEDANCE @ 200MHZ 925 Supplier Information Steward Corporate Office P.O. Box 510 Chattanooga, TN 37401-510 Phone: +1 (423) 308-1690 Phone: (800) 634-2673 - Toll Free Fax: +1 (423) 308-1622 Europe Brucefield Industrial Park Livingston EH%$ 9DR Scotland, UK Phone +44-[0]1-506-414200 Fax: +44-[0]1-506-410694 Asia 3791 Jalan Bukit Merah #10-14 E-Centre @ Redhill Singapore 159471 Phone: +65-6272-2646 Fax: +65-6272-6165 24 XRT83SL216 REV. 1.0.0 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT THE FOLLOWING TRANSFORMER IS RECOMMENDED FOR USE PART NUMBER T1113 VENDOR Pulse TURNS RATIO 1:2 Transmit 2:1 Receive PACKAGE TYPE TOU 2 Magnetic Supplier Information Supplier Information PULSE Corporate Office 12220 World Trade Drive San Diego, CA 92128 Tel: (619)-674-8100 FAX: (619)-674-8262 Europe 1 & 2 Huxley Road The Surrey Research Park Guildford, Surrey GU2 5RE United Kingdom Tel: 44-1483-401700 FAX: 44-1483-401701 Asia 150 Kampong Ampat #07-01/02 KA Centre Singapore 368324 Tel: 65-287-8998 FAX: 65-280-0080 25 XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 4.0 SERIAL MICROPROCESSOR INTERFACE BLOCK The serial microprocessor uses a standard 3-pin serial port with CS, SCLK, and SDI for programming the LIU. Optional pins such as SDO, INT, and RESET allow the ability to read back contents of the registers, monitor the LIU via an interrupt pin, and reset the LIU to its default configuration by pulling reset "Low" for more than 10S. A simplified block diagram of the Serial Microprocessor is shown in Figure 20. FIGURE 20. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE REV. 1.0.0 CS SCLK SDI Serial Microprocssor Interface SDO INT RESET FIGURE 21. MICROPROCESSOR SERIAL INTERFACE STRUCTURE CS SClk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SDI R/W A0 A1 A2 A3 A4 A5 0 D0 D1 D2 D3 D4 D5 D6 D7 High Z SDO D0 D1 D2 D3 D4 D5 D6 D7 High Z NOTE: If the R/W bit is set to "1", then this denotes a "READ" operation with the Microprocessor Serial Interface. Conversely, if the R/W bit is set to "0", then this denotes a "WRITE" operation. 26 XRT83SL216 REV. 1.0.0 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT FIGURE 22. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE t28 CS t21 t26 SCLK t22 SDI t23 R/W A0 A1 t24 t27 t25 CS SCLK t29 SDO Hi-Z D0 t30 D1 Don't Care (Read mode) t32 D2 D7 t31 SDI TABLE 5: MICROPROCESSOR SERIAL INTERFACE TIMINGS ( TA = 250C, VDD=3.3V 5% AND LOAD = 10PF) SYMBOL t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 PARAMETER CS Low to Rising Edge of SClk SDI to Rising Edge of SClk SDI to Rising Edge of SClk Hold Time SClk "Low" Time SClk "High" Time SClk Period Falling Edge of SClk to rising edge of CS CS Inactive Time Falling Edge of SClk to SDO Valid Time Falling Edge of SClk to SDO Invalid Time Rising edge of CS to High Z Rise/Fall time of SDO Output MIN. 5 5 5 50 50 100 0 50 TYP. MAX UNITS ns ns ns ns ns ns ns ns 20 10 25 5 ns ns ns ns 27 XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT TABLE 6: MICROPROCESSOR REGISTER DESCRIPTION REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0 REV. 1.0.0 Global Control Register for All 16 Channels (0x00h) 0 1 2 3 4 5 0x00 0x01 0x02 0x03 0x04 0x05 R/W RO RO RO RO RO GIE INTS7 INTS15 Reserved INTS6 INTS14 SR/DR INTS5 INTS13 CODE INTS4 INTS12 FIFO INTS3 INTS11 JABW INTS2 INTS10 JASEL1 INTS1 INTS9 JASEL0 INTS0 INTS8 Revision ID (See Bit Description) Device ID (See Bit Description) Device ID (See Bit Description) Channel 0 Control Register (0x04h - 0x06h) 6 7 8 0x06 0x07 0x08 R/W R/W RUR/ RO SRES_0 * Reserved Reserved ARAOS_0 AISIE_0 AISIS_0 ATAOS_0 DMOIE_0 DMOIS_0 TAOS_0 RLOSIE_0 RLOSIS_0 RLAM_0 Reserved Reserved TXOE_0 Reserved AISS_0 RCLKinv_0 LPB1 DMOS_0 TCLKinv_0 LPB0 RLOSS_0 Channel 1 Control Register (0x07h - 0x09h) 9 10 11 0x09 0x0A 0x0B R/W R/W RUR/ RO SRES_1 * Reserved Reserved ARAOS_1 AISIE_1 AISIS_1 ATAOS_1 DMOIE_1 DMOIS_1 TAOS_1 RLOSIE_1 RLOSIS_1 RLAM_1 Reserved Reserved TXOE_1 Reserved AISS_1 RCLKinv_1 LPB1 DMOS_1 TCLKinv_1 LPB0 RLOSS_1 Channel 2 Control Register (0x0Ah - 0x0Ch) 12 13 14 0x0C 0x0D 0X0E R/W R/W RUR/ RO SRES_2 * Reserved Reserved ARAOS_2 AISIE_2 AISIS_2 ATAOS_2 DMOIE_2 DMOIS_2 TAOS_2 RLOSIE_2 RLOSIS_2 RLAM_2 Reserved Reserved TXOE_2 Reserved AISS_2 RCLKinv_2 LPB1 DMOS_2 TCLKinv_2 LPB0 RLOSS_2 Channel 3 Control Register (0x0Dh - 0x0Fh) 15 16 17 0x0F 0x10 0x11 R/W R/W RUR/ RO SRES_3 * Reserved Reserved ARAOS_3 AISIE_3 AISIS_3 ATAOS_3 DMOIE_3 DMOIS_3 TAOS_3 RLOSIE_3 RLOSIS_3 RLAM_3 Reserved Reserved TXOE_3 Reserved AISS_3 RCLKinv_3 LPB1 DMOS_3 TCLKinv_3 LPB0 RLOSS_3 Channel 4 Control Register (0x10h - 0x12h) 18 19 20 0x12 0x13 0x14 R/W R/W RUR/ RO SRES_4 * Reserved Reserved ARAOS_4 AISIE_4 AISIS_4 ATAOS_4 DMOIE_4 DMOIS_4 TAOS_4 RLOSIE_4 RLOSIS_4 RLAM_4 Reserved Reserved TXOE_4 Reserved AISS_4 RCLKinv_4 LPB1 DMOS_4 TCLKinv_4 LPB0 RLOSS_4 Channel 5 Control Register (0x13h - 0x15h) 21 22 23 0x15 0x16 0x17 R/W R/W RUR/ RO SRES_5 * Reserved Reserved ARAOS_5 AISIE_5 AISIS_5 ATAOS_5 DMOIE_5 DMOIS_5 TAOS_5 RLOSIE_5 RLOSIS_5 RLAM_5 Reserved Reserved TXOE_5 Reserved AISS_5 RCLKinv_5 LPB1 DMOS_5 TCLKinv_5 LPB0 RLOSS_5 Channel 6 Control Register (0x16h - 0x18h) 28 XRT83SL216 REV. 1.0.0 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT TABLE 6: MICROPROCESSOR REGISTER DESCRIPTION REG 24 25 26 ADDR TYPE 0x18 0x19 0x1A R/W R/W RUR/ RO D7 SRES_6 * Reserved Reserved D6 ARAOS_6 AISIE_6 AISIS_6 D5 ATAOS_6 DMOIE_6 DMOIS_6 D4 TAOS_6 RLOSIE_6 RLOSIS_6 D3 RLAM_6 Reserved Reserved D2 TXOE_6 Reserved AISS_6 D1 RCLKinv_6 LPB1 DMOS_6 D0 TCLKinv_6 LPB0 RLOSS_6 Channel 7 Control Register (0x19h - 0x1Bh) 27 28 29 0x1B 0x1C 0x1D R/W R/W RUR/ RO SRES_7 * Reserved Reserved ARAOS_7 AISIE_7 AISIS_7 ATAOS_7 DMOIE_7 DMOIS_7 TAOS_7 RLOSIE_7 RLOSIS_7 RLAM_7 Reserved Reserved TXOE_7 Reserved AISS_7 RCLKinv_7 LPB1 DMOS_7 TCLKinv_7 LPB0 RLOSS_7 Channel 8 Control Register (0x1Ch - 0x1Eh) 30 31 32 0x1E 0x1F 0x20 R/W R/W RUR/ RO SRES_8 * Reserved Reserved ARAOS_8 AISIE_8 AISIS_8 ATAOS_8 DMOIE_8 DMOIS_8 TAOS_8 RLOSIE_8 RLOSIS_8 RLAM_8 Reserved Reserved TXOE_8 Reserved AISS_8 RCLKinv_8 LPB1 DMOS_8 TCLKinv_8 LPB0 RLOSS_8 Channel 9 Control Register (0x1Fh - 0x21h) 33 34 35 0x21 0x22 0x23 R/W R/W RUR/ RO SRES_9 * Reserved Reserved ARAOS_9 AISIE_9 AISIS_9 ATAOS_9 DMOIE_9 DMOIS_9 TAOS_9 RLOSIE_9 RLOSIS_9 RLAM_9 Reserved Reserved TXOE_9 Reserved AISS_9 RCLKinv_9 LPB1 DMOS_9 TCLKinv_9 LPB0 RLOSS_9 Channel 10 Control Register (0x22h - 0x24h) 36 37 38 0x24 0x25 0x26 R/W R/W RUR/ RO SRES_10 * Reserved Reserved ARAOS_10 AISIE_10 AISIS_10 ATAOS_10 DMOIE_10 DMOIS_10 TAOS_10 RLOSIE_10 RLOSIS_10 RLAM_10 Reserved Reserved TXOE_10 Reserved AISS_10 RCLKinv_10 LPB1 DMOS_10 TCLKinv_10 LPB0 RLOSS_10 Channel 11 Control Register (0x25h - 0x27h) 39 40 41 0x27 0x28 0x29 R/W R/W RUR/ RO SRES_11 * Reserved Reserved ARAOS_11 AISIE_11 AISIS_11 ATAOS_11 DMOIE_11 DMOIS_11 TAOS_11 RLOSIE_11 RLOSIS_11 RLAM_11 Reserved Reserved TXOE_11 Reserved AISS_11 RCLKinv_11 LPB1 DMOS_11 TCLKinv_11 LPB0 RLOSS_11 Channel 12 Control Register (0x28h - 0x2Ah) 42 43 44 0x2A 0x2B 0x2C R/W R/W RUR/ RO SRES_12 * Reserved Reserved ARAOS_12 AISIE_12 AISIS_12 ATAOS_12 DMOIE_12 DMOIS_12 TAOS_12 RLOSIE_12 RLOSIS_12 RLAM_12 Reserved Reserved TXOE_12 Reserved AISS_12 RCLKinv_12 LPB1 DMOS_12 TCLKinv_12 LPB0 RLOSS_12 Channel 13 Control Register (0x2Bh - 0x2Dh) 45 46 47 0x2D 0x2E 0x2F R/W R/W RUR/ RO SRES_13 * Reserved Reserved ARAOS_13 AISIE_13 AISIS_13 ATAOS_13 DMOIE_13 DMOIS_13 TAOS_13 RLOSIE_13 RLOSIS_13 RLAM_13 Reserved Reserved TXOE_13 Reserved AISS_13 RCLKinv_13 LPB1 DMOS_13 TCLKinv_13 LPB0 RLOSS_13 29 XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT TABLE 6: MICROPROCESSOR REGISTER DESCRIPTION REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0 REV. 1.0.0 Channel 14 Control Register (0x2Eh - 0x30h) 48 49 50 0x30 0x31 0x32 R/W R/W RUR/ RO SRES_14 * Reserved Reserved ARAOS_14 AISIE_14 AISIS_14 ATAOS_14 DMOIE_14 DMOIS_14 TAOS_14 RLOSIE_14 RLOSIS_14 RLAM_14 Reserved Reserved TXOE_14 Reserved AISS_14 RCLKinv_14 LPB1 DMOS_14 TCLKinv_14 LPB0 RLOSS_14 Channel 15 Control Register (0x31h - 0x33h) 51 52 53 0x33 0x34 0x35 R/W R/W RUR/ RO SRES_15 * Reserved Reserved ARAOS_15 AISIE_15 AISIS_15 ATAOS_15 DMOIE_15 DMOIS_15 TAOS_15 RLOSIE_15 RLOSIS_15 RLAM_15 Reserved Reserved TXOE_15 Reserved AISS_15 RCLKinv_15 LPB1 DMOS_15 TCLKinv_15 LPB0 RLOSS_15 NOTE: * Indicates that these bits are WRITE-ONLY Reset for that channel register only. TABLE 7: MICROPROCESSOR REGISTER 0X00H BIT DESCRIPTION GLOBAL CONTROL REGISTER FOR ALL 16 CHANNELS (0X00H) Register Type Default Value (HW reset) 0 BIT NAME FUNCTION D7 GIE Global Interrupt Enable The global interrupt enable is used to enable/disable all interrupt activity for all 16 channels. This bit must be set "High" for the interrupt pin to operate. "0" = Disable all interrupt generation "1" = Enable interrupt generation to the individual channel registers R/W D6 D5 Reserved SR/DR This Register Bit is Not Used R/W R/W 0 0 Single Rail / Dual Rail Select This bit is used to configure the receive outputs and transmit inputs to single rail or dual rail data formats. "0" = Dual Rail "1" = Single Rail D4 CODE Encoding / Decoding Select (Single Rail Mode Only) This bit is used to select between AMI or HDB3. "0" = HDB3 "1" = AMI R/W 0 D3 FIFOS FIFO Depth Select The FIFO depth select is used to configure the part for a 32-bit or 64-bit FIFO (Within the Jitter Attenuator Block). The delay of the FIFO is typically equal to 1/2 the FIFO depth. "0" = 32-bit FIFO "1" = 64-bit FIFO R/W 0 30 XRT83SL216 REV. 1.0.0 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT TABLE 7: MICROPROCESSOR REGISTER 0X00H BIT DESCRIPTION GLOBAL CONTROL REGISTER FOR ALL 16 CHANNELS (0X00H) Register Type Default Value (HW reset) 0 BIT NAME FUNCTION D2 JABW JA Band width Select This bit is used to select the band with of the JA PLL. "0" = 10 Hz "1" = 1.5Hz NOTE: If a "1" is written into this bit, JA FIFO size of 64 bit wide is automatically selected. R/W D1 D0 JASEL1 JASEL0 Jitter Attenuator Select These bits are used to configure the Jitter Attenuator into the Receive or Transmit path. "00" = Disabled "01" = Transmit Path "10" = Receive Path "11" = Disabled R/W 0 0 TABLE 8: MICROPROCESSOR REGISTERS 0X01H &0X02H BIT DESCRIPTION INTERRUPT STATUS REGISTERS (0X01H) & 0X02H Register Type Default Value (HW reset) 0 0 0 0 0 0 0 0 BIT NAME FUNCTION D7 D6 D5 D4 D3 D2 D1 D0 INTS_n Interrupt Status These 2 registers are ready only to determine when an interrupt event occurs, the channel that generates interrupt can be identified with minimum read/write operation. RO 31 XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT TABLE 9: MICROPROCESSOR REGISTER 0X03H BIT DESCRIPTION REVISION "ID" REGISTER (0X03H) Register Type Default Value (HW reset) 0 0 0 0 0 0 0 1 REV. 1.0.0 BIT NAME FUNCTION D7 D6 D5 D4 D3 D2 D1 D0 Revision "ID" The revision "ID" of the XRT83SL216 LIU is used to enable software to identify which revision of silicon is currently being tested. The revision "ID" for the first revision of silicon (Revision A) will be 0x01h. RO TABLE 10: MICROPROCESSOR REGISTERS 0X04H & 0X05H BIT DESCRIPTION DEVICE "ID" REGISTERS (0X04H & 0X05H) Register Type Default Value (HW reset) BIT NAME FUNCTION D7 D6 D5 D4 D3 D2 D1 D0 Device "ID" The device for this chip consists of 2 read only registers. The ID for the XR T83SL216 is 0x8004h. RO TABLE 11: MICROPROCESSOR REGISTER BIT DESCRIPTION CHANNEL CONTROL REGISTER (CHANNEL_n, where n = 0:15) (0X06H, 0X09H, 0X0CH, 0X0FH, 0X12H, 0X15H, 0X18H, 0X1BH, 1EH, 0X21H, 0X24H, 0X27H, 0X2AH, 0X2DH, 0X30H, 0X33H) Register Type Default Value (HW reset) X BIT NAME FUNCTION D7 SRES_n Software Reset Writing a "1" to this bit will cause the channel register to reset to it's default value. NOTE: This is a Write-Only bit. WO D6 ARAOS_n Automatic Receive All Ones If ARAOS_n is selected, an all ones pattern will be sent to the RPOS/RNEG outputs if the channel experiences an RLOS condition. If RLOS does not occur, ARAOS_n will remain inactive. "0" = Disabled "1" = Enabled R/W 0 32 XRT83SL216 REV. 1.0.0 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT TABLE 11: MICROPROCESSOR REGISTER BIT DESCRIPTION CHANNEL CONTROL REGISTER (CHANNEL_n, where n = 0:15) (0X06H, 0X09H, 0X0CH, 0X0FH, 0X12H, 0X15H, 0X18H, 0X1BH, 1EH, 0X21H, 0X24H, 0X27H, 0X2AH, 0X2DH, 0X30H, 0X33H) Register Type Default Value (HW reset) 0 BIT NAME FUNCTION D5 ATAOS_n Automatic Transmit All Ones If ATAOS_n is selected, an all ones pattern will be transmitted from TTIP/TRING if the channel experiences an RLOS condition. If RLOS does not occur, ATAOS_n will remain inactive. "0" = Disabled "1" = Enabled R/W D4 TAOS_n Transmit All Ones If TAOS_n is selected, an all ones pattern will be transmitted from TTIP/TRING if the transmitter is turned on. Remote Loop Back has priority over TAOS. "0" = Disabled "1" = Enabled R/W 0 D3 RLAM_n RLOS/AIS Mode Select for channel n This bit is used to select the industry standard for declaring / clearing RLOS and AIS functionality. See the Receive section of the Line Interface description. "0" = ITU G.775 "1" =ETSI300233 R/W 0 D2 TXOE_n Transmit Output Enable Upon power up, the tranmitters are tri-stated. This bit is used to enable the transmitter for this channel if the TxOE pin is pulled "High". If the TxOE pin is pulled "Low", all 8 transmitters are tristated. "0" = Transmitter is disabled "1" = Transmitter is enabled if TxOE pin is pulled "High" R/W 0 D1 RCLKinv_n Receiver Clock Invert This bit is used to invert receive clock update edge with respect to RPOS/RNEG output data. "0" =RPOS/RNEG data is updated on the rising edge of RCLK "1" =RPOS/RNEG data is updated on the falling edge of RCLK. R/W 0 0 D0 TCLKinv_n Transmit Clock Invert This bit is used to invert transmit clock sampling edge with respect to TPOS/TNEG input data. "0" =TPOS/TNEG data is sampled on the falling edge of TCLK "1" =TPOS/TNEG data is sampled on the rising edge of TCLK. R/W 0 33 XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT TABLE 12: MICROPROCESSOR REGISTER BIT DESCRIPTION CHANNEL CONTROL REGISTER (CHANNEL_n, where n = 0:15) (0X07H, 0X0AH, 0X0DH, 0X10H, 0X13H, 0X16H, 0X19H, 0X1CH, 0X1FH, 0X22H, 0X25H, 0X28H, 0X2BH, 0X2EH, 0X31H, 0X34H) Register Type Default Value (HW reset) X 0 REV. 1.0.0 BIT NAME FUNCTION D7 D6 Reserved AISIE_n This Register Bit is Not Used X R/W Alarm Indication Signal Interrupt Enable "0" = Masks the AIS interrupt generation "1" = Enables Interrupt generation Driver Monitor Output Interrupt Enable "0" = Masks the DMO interrupt generation "1" = Enables Interrupt generation D5 DMOIE_n R/W 0 D4 RLOSIE_n Receiver Loss of Signal Interrupt Enable "0" = Masks the RLOS interrupt generation "1" = Enables Interrupt generation Reserved Reserved LPB1 LPB0 This Register Bit is Not Used This Register Bit is Not Used R/W 0 D3 D2 D1 D0 X X R/W X X 0 Loop Back Select These bits are used to configure the channel in one of three loopback modes. For additional information on loopback modes, see the Application Section of this datasheet. LPB1 0 0 1 1 LPB0 0 1 0 1 Loopback Mode No Loopback Analog Loopback Remote Loopback Digital Loopback TABLE 13: MICROPROCESSOR REGISTER BIT DESCRIPTION CHANNEL CONTROL REGISTER (CHANNEL_n, where n = 0:15) (0X08H, 0X0BH, 0X0EH, 0X11H, 0X14H, 0X17H, 0X1AH, 0X1DH, 0X20H, 0X23H, 0X26H, 0X29H, 0X2CH, 0X2FH, 0X32H, 0X35H) Register Type Default Value (HW reset) X 0 BIT NAME FUNCTION D7 D6 Reserved AISIS_n This Register Bit is Not Used R/W RUR Alarm Indication Signal Interrupt Status "0" = No Change "1" = Change in Status Occured 34 XRT83SL216 REV. 1.0.0 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT TABLE 13: MICROPROCESSOR REGISTER BIT DESCRIPTION CHANNEL CONTROL REGISTER (CHANNEL_n, where n = 0:15) (0X08H, 0X0BH, 0X0EH, 0X11H, 0X14H, 0X17H, 0X1AH, 0X1DH, 0X20H, 0X23H, 0X26H, 0X29H, 0X2CH, 0X2FH, 0X32H, 0X35H) Register Type Default Value (HW reset) 0 BIT NAME FUNCTION D5 DMOIS_n Driver Monitor Output Interrupt Status "0" = No Change "1" = Change in Status Occured RUR D4 RLOSSI_n Receiver Loss of Signal Interrupt Status "0" = No Change "1" = Change in Status Occured Reserved AISS_n This Register Bit is Not Used AIS Alarm Status This alarm indication signal detection is always active regardless if the interrupt generation is disabled. This bit indicates the AIS activity at the time of reading. "0" = No Alarm "1" = An All "Ones" Signal is detected. RUR 0 D3 D2 R/W RO X 0 D1 DMOS_n Driver Monitor Output Status The Driver Monitor output is always active regardless if the interrupt generation is disabled. This bit indicates the DMO output activity at the time of reading. "0" = No alarm "1" = Failure at the transmit output is detected. RO 0 D0 RLOSS_n Receive Loss of Signal Status The receiver loss of signal detection is always active regardless if the interrupt generation is disabled. This bit indicates the RLOS activity at the time of reading. "0" = No Alarm "1" = Loss of Signal condition is detected. RO 0 35 XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT ELECTRICAL CHARACTERISTICS TABLE 14: ABSOLUTE MAXIMUM RATINGS Storage Temperature Operating Temperature Supply Voltage -65C to +150C -40C to +85C -0.5V to +6.0V REV. 1.0.0 TABLE 15: DC DIGITAL INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS VDD=3.3V 5%, TA=25C, UNLESS OTHERWISE SPECIFIED PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage Output High Voltage IOH=2.0mA Output Low Voltage IOL=2.0mA Input Leakage Current Input Capacitance Output Lead Capacitance SYMBOL VDD VIH VIL VOH VOL IL CI CL MIN 3.13 2.0 -0.5 2.4 TYP 3.3 5.0 25 0.4 10 MAX 3.46 5.0 0.8 UNITS V V V V V A pF pF NOTE: Input leakage current excludes pins that are internally pulled "Low" or "High". TABLE 16: AC ELECTRICAL CHARACTERISTICS VDD=3.3V 5%, TA=25C, UNLESS OTHERWISE SPECIFIED PARAMETER MCLK Clock Duty Cycle MCLK Clock Tolerance SYMBOL MIN 40 TYP 50 MAX 60 UNITS % ppm TABLE 17: POWER CONSUMPTION VDD=3.3V 5%, TA=25C, UNLESS OTHERWISE SPECIFIED MODE E1 IMPEDANCE 75 RECEIVER 2:1 TRANSMITTER 1:2 TYP 1.6 2.3 1.4 1.9 400 MAX UNIT W TEST CONDITION 50% ones 100% ones 50% ones 100% ones Transmitter OFF E1 120 2:1 1:2 W E1 75/120 2:1 1.2 mW 36 XRT83SL216 REV. 1.0.0 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT TABLE 18: RECEIVER ELECTRICAL CHARACTERISTICS VDD=3.3V 5%, TA=25C, UNLESS OTHERWISE SPECIFIED PARAMETER MIN TYP MAX UNIT TEST CONDITION Receiver Loss of Signal Number of consecutive zeros before RLOS is declared Input signal level at RLOS RLOS clear Receiver Sensitivity (flat loss only) 15 12.5 11 32 2048 20 13 dB % ones dB G.775 ETSI 300 233 Cable attenuation @ 1024kHz ITU-G.775, ETSI 300 233 With nominal pulse amplitude of 3.0V for 120 and 2.37V for 75. With -18dB interference signal added. With 6dB cable loss. k Interference Margin Input Impedance Input Jitter Tolerance 1Hz 10kHz - 100kHz Recovered Clock Jitter Transfer Corner Frequency Peaking Amplitude Jitter Attenuator Corner Frequency JABW = "0" JABW = "1" Return Loss 51kHz - 102kHz 102kHz - 2048kHz 2048kHz - 3072kHz -18 - -14 15 37 0.2 - - UIp-p UIp-p ITU-G.823 - 36 - +0.5 kHz dB - 10 1.5 - Hz Hz 14 20 16 - - dB dB dB ITU-G.703 37 XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT TABLE 19: E1 TRANSMITTER ELECTRICAL CHARACTERISTICS VDD=3.3V 5%, TA=25C, UNLESS OTHERWISE SPECIFIED PARAMETER AMI Output Pulse Amplitude 75 120 Output Pulse Width Output Pulse Width Ratio Output Pulse Amplitude Ratio Jitter Added by the Transmitter Output Output Return Loss 51kHz - 102kHz 102kHz - 2048kHz 2048kHz - 3072kHz MIN TYP MAX UNIT TEST CONDITION REV. 1.0.0 2.13 2.70 224 0.95 0.95 - 2.37 3.00 244 0.025 2.60 3.30 264 1.05 1.05 0.05 V V ns 1:2 Transformer ITU-G.703 ITU-G.703 UIp-p Broad Band with jitter free TCLK applied to the input. 12 10 8 - - dB dB dB ETSI 300 166 NOTE: Transmit output return loss is dependent on the transformer characteristics. 38 XRT83SL216 REV. 1.0.0 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT ORDERING INFORMATION PRODUCT NUMBER XRT83SL216IB PACKAGE 289 ball STBGA OPERATING TEMPERATURE RANGE -400C to +850C PACKAGE DIMENSIONS FIGURE 23. 15X15MM 289 BALL STBGA Note: The control dimension is in millimeter. INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.056 0.067 1.42 1.70 A1 0.010 0.014 0.25 0.35 A2 0.046 0.053 1.17 1.35 D 0.583 0.598 14.80 15.20 D1 0.504 BSC 12.80 BSC b 0.015 0.019 0.37 0.47 e 0.0315 BSC 0.80 BSC 39 XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REVISION HISTORY REVISION # P1.0.0 P1.0.1 P1.0.2 P1.0.3 1.0.0 DATE 07/07/05 08/04/05 11/05 12/06/05 08/02/06 DESCRIPTION First release of the 16-Channel LIU Preliminary Datasheet Edits to features, RNEG description,figure 6,, electrical supply voltage. Edits Changed receive transformer turns ratio from 1:1 to 2:1. Added register information.Table 16: Power Consumption added TYP values. Removed TBD's from electrical, removed preliminary and updated document format. Added timing diagram and timing info for the microprocessor serial interface. REV. 1.0.0 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2006 EXAR Corporation Datasheet August 2006. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 40 |
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